/*
 * Dummy file to start a Chisel project.
 *
 * Author: Martin Schoeberl (martin@jopdesign.com)
 * 
 */

package empty

import chisel3._
import chisel3.util._

class Count extends Module{
  val io = IO (new Bundle{
    val en    = Input(Bool())
    val valid = Output(Bool())
    val out1   = Output(UInt(8.W))
    val out2   = Output(UInt(8.W))
  })

  val (a,b) = Counter(io.en, 233)
  io.out1   := a                         //计数器的计数值
  io.valid := b                          //达到最大值的指示信号

  val counter = Counter(3)               //达到2时清零
  when(io.en){
   counter.inc()                         //调用inc方法，使计数器+1
  }
  io.out2 := counter.value
}

object Count extends App {
  println("Generating the adder hardware")
  emitVerilog(new Count(), Array("--target-dir", "generated/ChiselStudy/Count"))
}